1. Field of the Invention
The present invention relates to decoder circuitry and a reproducing apparatus. More particularly, it relates to decoder circuitry with an A/D (analog-to-digital) converter as is well suited to a recording/reproducing apparatus, e.g., a magnetic disk drive. It also relates to such a reproducing apparatus.
2. Description of Related Art
In a magnetic recording/reproducing apparatus typified by a magnetic disk drive, high-density recording has advanced year by year to realize larger storage capacities. Besides, user needs and higher-density recording have made the transfer rate of data higher and the size of the apparatus smaller.
For realizing the higher performance and smaller size of the apparatus, it is indispensable to implement electronic circuits in the form of an LSI (large-scale integrated circuit). The LSI implementation is very useful for reducing the number of components and the packaging area of the apparatus and for enhancing the performance and the functions thereof. In a recent magnetic disk drive, an analog/digital hybrid LSI, in which a plurality of functional parts for handling analog signals and a plurality of functional parts for handling digital signals are put into a single chip together, is utilized owing to the progress of semiconductor technology. Typical is a read/write signal processing LSI.
Read/write signal processing systems contribute greatly to the higher-density recording. Recently, data reproduction processing systems which utilize partial response based on maximum likelihood detection (PRML: Partial Response Maximum Likelihood) are being put into practical use. An example of a circuit arrangement conforming to the PRML system is disclosed in FIG. 3 of U.S. Pat. No. 5,233,482 entitled "THERMAL ASPERITY COMPENSATION FOR PRML DATA DETECTION". Other examples are techniques stated in the official gazettes of Japanese Patent Applications Laid-Open (Kokai) Nos. 1-143447 and No. 61-129913.
FIG. 15 of the accompanying drawings illustrates the schematic construction of a prior-art magnetic disk drive which employs PRML. The magnetic disk drive shown in FIG. includes a magnetic head 2 which records signal information on a magnetic recording medium 1 in the form of a magnetic signal and which converts a magnetic signal on the magnetic recording medium 1 into an electric signal, an actuator 3 which moves the magnetic head 2 in cases of a tracking control and access control, and a preamplifier 4 which sends a write data signal to the magnetic head 2 and which amplifies an electric signal reproduced by the magnetic head 2. The magnetic disk drive also includes a readout module 5 consisting of a voltage-controlled type variable-gain amplifier (VGA) 6 which controls the signal amplified by the preamplifier 4, to an appropriate amplitude at all times, and then delivers the controlled signal, and a filter 7 which eliminates noise from within the reproduced signal controlled to the predetermined amplitude by the VGA 6. An A/D (analog-to-digital) converter 8 is included in order to convert the output 102 of the filter 7 into a digital signal. Also included is an equalization module 9 consisting of an equalizer 10 which is constructed of a digital transversal filter for performing Nyquist equalization of the digital signal converted by the A/D converter 8, and a PR processor (constructed of a 1+D! circuit) 11 which subjects the output of the equalizer 10 to "PR4" (Partial Response Class-4) processing. Further included is a decoding module 17 consisting of a Viterbi detector 18 which subjects the output of the PR processor 11 to Viterbi detection, and a decoder 19 which decodes the output data of the Viterbi detector 18. The magnetic disk drive also includes a disk controller 24 which transfers data between this disk drive and a host computer (not shown) being a host apparatus, and which controls the various blocks of this disk drive. It also includes a servo positioning detector 25 which serves to position the magnetic head 2 on the basis of the filter output 102, an actuator controller 26 which receives the output of the servo positioning detector 25 and then delivers an actuator control signal, and an actuator driver 27 which receives the actuator control signal and then drives the actuator 3. A PLL (phase-locked loop) controller 16 is included in order to generate a sampling clock 101 which is used when the filter output 102 is converted into the digital signal by the A/D converter 8. Also included is an AGC (automatic gain control) module 12 consisting of an AGC circuit 13 which controls the amplitude of the reproduced signal to an appropriate value, a switching circuit 14 which switches the outputs of the AGC circuit 13, and an integrator 15 which integrates the output current of the switching circuit 14 and then delivers a control current for the gain adjustment of the VGA 6. Further included is a recording module 20 consisting of an encoder 23 which encodes data delivered from the disk controller 24, a precoder 22 which affords interference characteristics reverse to the PR equalization on the reproduction side, and a write pre-compensator 21 which compensates for a magnetizing interference. A microprocessor 28 is included in order to control the whole disk drive.
Referring to FIG. 15, when data is to be reproduced, the electrical signal reproduced by the magnetic head 2 is passed through the preamplifier 4, VGA 6 and filter 7 and is converted into the digital signal by the A/D converter 8. The timing at which the filter output 102 is converted into the digital signal by the A/D converter 8, is controlled into an appropriate phase by the PLL controller 16. The output of the A/D converter 8 thus produced is passed through the equalizer 10 and PR processor 11. Thereafter, the resulting signal is detected by the Viterbi detector 18 and is decoded by the decoder 19. Subsequently, the decoded signal is delivered to the disk controller 24. The AGC module 12 controls the gain of the VGA 6 to an appropriate value.
Generally, in a magnetic disk drive, an A/D converter is necessitated for adopting the PRML signal processing system. The A/D converter of high speed and high accuracy, however, dissipates a lot of power. Moreover, the data transfer rate of the magnetic disk drive heightens abruptly, and the frequencies of signals to be handled by this disk drive increase. That is, the magnetic disk drive requires analog circuits of wide bands and high accuracies and digital circuits capable of fast operations. Accordingly, the dissipation power of the magnetic disk drive increases inevitably, and the read/write signal processing LSI thereof becomes difficult to implement as a single chip. Therefore, the PRML signal processing has heretofore been coped with by externally mounting the A/D converter or by employing a multichip layout.
As shown in FIG. 16, the read/write signal processing LSI of the prior-art magnetic disk drive has a two-chip layout configured of an analog-group LSI in which the A/D converter etc. for handling analog signals are integrated, and a digital-group LSI in which the equalizer etc. for handling digital signals are integrated.
Problems to be stated below are involved in the signal processing semiconductor IC (integrated circuit) including the A/D converter in the prior art.
With conventional semiconductor technology, the signal processing semiconductor IC is configured of the plurality of LSIs for a data transfer rate of, at least, about 80 (Mbits/second). This poses the problem that I/O (input/output) buffers for I/O signals to be exchanged between the LSI's dissipate a lot of power. The configuration of the plurality of LSIs also poses the problem that losses arise in the signals of data which are exchanged between inputs and outputs, so the transfers of the data are difficult to speed up. That is, the sampling performance of the A/D converter degrades with the data transfer rate. In the signal processing semiconductor IC in the prior art, the number of bits of the A/D converter is set at 6 or larger for the data transfer rate of, at least, about 80 (Mbits/second). Therefore, the single-chip implementation of the signal processing semiconductor IC is very difficult from the viewpoint of power dissipation.